By Ben U Seng Pan, Rui Paulo da Silva Martins, Jose de Albuquerque Epifanio da Franca
Design of Very High-Frequency Multirate Switched-Capacitor Circuits provides the speculation and the corresponding CMOS implementation of the unconventional multirate sampled-data analog interpolation strategy which has its nice power on very high-frequency analog frond-end filtering as a result of its inherent twin good thing about decreasing the rate of data-converters and DSP middle including the specification leisure of the submit continuous-time filtering. this method thoroughly removes the conventional phenomenon of sampled-and-hold frequency-shaping on the decrease enter sampling fee. additionally, as a way to take on actual IC imperfections at very excessive frequency, the cutting-edge circuit layout and format concepts for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed:
-Optimum circuit structure tradeoff analysis
-Simple velocity and tool trade-off research of lively elements
-High-order filtering reaction accuracy with appreciate to capacitor-ratio mismatches
-Time-interleaved influence with appreciate to realize and offset mismatch
-Time-interleaved impression with recognize to timing-skew and random jitter with non-uniformly holding
-Stage noise research and allocation scheme
-Substrate and provide noise reduction
-Gain-and offset-compensation techniques
-High-bandwidth low-power amplifier layout and layout
-Very low timing-skew multiphase generation
Two tailored optimal layout examples in CMOS are provided. the 1st one achieves a 3-stage 8-fold SC interpolating clear out with 5.5MHz bandwidth and 108MHz output sampling fee for a NTSC/PAL CCIR 601 electronic video at three V. one other is a 15-tap 57MHz SC FIR bandpass interpolating filter out with 4-fold sampling cost raise to 320MHz and the first-time embedded frequency band up-translation for DDFS approach at 2.5V. The corresponding chip prototype achieves to date the top working frequency, optimum filter out order and optimum heart frequency with optimum dynamic variety lower than the bottom provide voltage compared to the formerly mentioned high-frequency SC filters in CMOS.
Read or Download Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering PDF
Similar design books
Der Rat für Formgebung hat seinen Sitz in Frankfurt am major.
Designing and development injection molds shouldn't be a dear trial and blunder technique. in attaining powerful mould building the proper manner via relating this 3rd installment within the bestselling sequence. This booklet courses readers in disposing of guesswork with serious mould layout equivalent to gate place, form and dimension.
- The Language of Architecture: 26 Principles Every Architect Should Know
- Design of System on a Chip: Devices & Components
- VLSI Design for Manufacturing: Yield Enhancement
- High Data Rate Transmitter Circuits: RF CMOS Design and Techniques for Design Automation
- Interconnect-Centric Design for Advanced SOC and NOC
- Engineering Design Handbook - Military Pyrotechnics Series, Part Three - Properties of Materials Used in Pyrotechnic Compositions
Extra info for Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering
14c) and It is obvious that a non-canonic structure requires fewer, though relatively high-speed, amplifiers due to the reduced number of ADB’s and single accumulator. On the contrary, the canonic structure needs more, though slower, opamps, like in the FIR counterparts. 13], thus will all succeed in the inherent immunity to the input lower-rate S/H shaping distortion. 2 SC Circuit Architectures To generalize with simplicity, only SC circuitry for a recursive-ADB structure will be presented for the IIR interpolating filter, since the nonrecursive ADB realization for the FIR function can be easily obtained only by removing the feedback recursive networks.
Polyphase filter m=0 h0 h2z-2 x[nTs] 1 ¦ xit[nTit] m=1 fs 2fs h1 z-1 – unit delay period Tit Input S/H Signal x[2Ts] x[Ts] x Ts Output Interpolated Signal ... Original Input Analog Signal Tit xit[2Tit] xit[3Tit] xit[4Tit] xit[5Tit] x[Ts]h1 x[Ts]h0+xh2 ... x[2Ts]h1 x[2Ts]h0+x[Ts]h2 Figure 2-3. Improved analog interpolation with Optimum-class realization by Direct-Form polyphase structure (L=2) 22 Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries of CMOS Analog Front-End Filtering In general, it is concluded that the DF polyphase interpolation, with original digital prototype transfer function, implements an improved analog interpolation without the input S/H filtering effect.
Shieu, “Non-recursive Switched-Capacitor decimator and interpolator circuits,” in Proc. 1215-1218, 1992. Takebe, “SC FIR interpolation filters using parallel cyclic networks,” in Proc. 723-726, 1994. Franca, “Switched-capacitor interpolator for direct-digital frequency synthesizers,” in Proc. 228 -231, 1998. , NJ, 1983. , 1993. Chapter 2 IMPROVED MULTIRATE POLYPHASE-BASED INTERPOLATION STRUCTURES 1. INTRODUCTION The design of improved SC structures for interpolating filtering embraces first the speed relaxation and number reduction of the opamps in the circuit for the optimum-class multirate realization, and secondly the elimination of the input lower-rate S/H shaping effect which then leads the SDA interpolation to operate in a similar manner as its digital counterpart.