By Muhammad S. Elrabaa
Advanced Low-Power electronic Circuit Techniques provides a number of novel excessive functionality electronic circuit designs that emphasize low-power and low-voltage operation. those circuits signify a variety of circuits which are utilized in state of the art VLSI structures and for this reason function strong examples for low-power layout. each one bankruptcy includes a short advent that serves as a short historical past and provides the inducement at the back of the layout. every one bankruptcy additionally ends with a precis that in short explains the contributions contained therein. This makes the e-book very readable. The reader can skim throughout the chapters in a short time to get a suppose for the layout difficulties awarded within the booklet and the options proposed by means of the authors. Examples of circuits utilized in platforms the place low-power is critical from reliability and portability issues of view (such as general-purpose and DSP processors) are offered in Chapters 2, three and four. Chapters five and seven supply examples of circuits utilized in platforms the place reliability and extra approach integration are the most using forces in the back of decreasing the facility intake. bankruptcy 6 provides an instance of a normal function high-performance low-power circuit layout.
Advanced Low-Power electronic Circuit Techniques is a true designer's ebook. It investigates substitute circuit kinds, in addition to architectural choices, and provides quantitative effects for comparability in reasonable applied sciences. numerous of the circuits offered were fabricated in order that simulations could be checked. The circuits lined are crucial development blocks for lots of designs, so the textual content could be of direct use to designers. MOS designs are lined, in addition to BiCMOS, and there are numerous novel circuits.
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Extra info for Advanced Low-Power Digital Circuit Techniques
Sinc e the adder is a stand alone application and is independent from the multiplier design, devoting a sep erate Chapter for it is justifi ed. Finally the goal of this work is to devise novel low-power , low-voltag e circuit techniques whi ch can be used in implementing multipliers in general. A Booth multiplier is used to demonstrate the performan ce of su ch circuits. Hence, com parison with other multipliers is not included. 2 a review of some of the existing parall el multipliers is pr esented .
Thus, improving the throughpu t of this al gori th m requires a high-performan ce multiplier. Tr aditi onally in order to achi eve high pe rformance multipliers, parall el add ition of th e parti al pro d uc ts is used along with redu cin g the t echn ology feature size. In th e past, m ost of the research and design efforts have focused on increasin g t he speed and throu ghput of DSPs. As a result, pr esent technologies po sses comput ing capa cit ies th at a llow the realiz ation of com putationally intensive t asks such as speech recognition and real time digital vid eo.
A Booth multiplier is used to demonstrate the performan ce of su ch circuits. Hence, com parison with other multipliers is not included. 2 a review of some of the existing parall el multipliers is pr esented . A comparison of th e various ar chitectures is also given. 3 th e circuit archite ct ure and simulat ion m ethod used is described. 7 the design and optimization of th e multiplier building block are discussed. 8 th e simulation results for a 6-bit modified Booth multiplier is pres ented.